The present invention relates to the field of electronic design and testing, and specifically to the field of generation of analog test signals for device testing.
Mixed-signal devices require synchronized analog and digital signals to be sourced to the Device-Under-Test (xe2x80x9cDUTxe2x80x9d) for comprehensive test coverage. Linear DUTs also require analog signals to be sourced as input for complete test coverage. These mixed analog and digital signals are known as test stimuli. Both types of devices require input waveforms which are extremely difficult to generate. The problem is increasingly difficult when attempting to test such devices with a VLSI digital tester.
The analog signal and mixed signal (digital patterns that work in combination with analog signals) portions of test programs are typically generated by a test engineer. The test engineer uses mostly manual processes to create and measure sine waves, current, DC voltages, and digital patterns to exercise the analog and mixed-signal portions of the DUT. Consequently, generation of analog and mixed-signal test programs is still a laborious and manual process.
The traditional solution to generating the waveforms needed to fit the analog portion of a test program is to add an expensive Arbitrary Waveform Generator (or xe2x80x9cAWGxe2x80x9d), such as the HP E1441A by Hewlett Packard, to a digital tester unit. Typically, an AWG such as the HP E1441A can output standard waveforms: sine, square, triangle, ramp, and noise. The AWG also allows custom design of waveforms. Any waveform generated can be modulated using AM, FM, FSK, or other forms of modulation. Frequency sweeping is also typically available. The number of datapoints defined in the waveform (or xe2x80x9cthe resolution of the waveformxe2x80x9d) is also subject to user control in the AWG.
FIG. 2 depicts the connection of a digital tester unit to both an AWG and a DUT. The VLSI Digital Tester initiates and controls the generation of waveforms needed to test the DUT. Communication of the VLSI Digital Tester unit with the DUT depends upon the design of the DUT. Generally, an electronic interconnection, such as Testhead 102 is constructed as the interface between the output pins of the VLSI Digital Tester unit and the input pins of the DUT. The interface can include additional hardware which further modifies the output of the digital tester unit. A device interface board 104 is used to connect the Testhead 102 to the DUT. The Tester Control Computer controls both the AWG and the VLSI Digital Tester while a test program is administered. The AWG must also be in communication with the VLSI digital tester unit. The VLSI digital Tester and the AWG are connected in order to synchronize the output of the AWG (input to the DUT) with the VLSI Digital Tester. As FIG. 2 reveals, one source of problems for the test engineer in utilizing an AWG is cabling. When setting up a test of a device type that uses AWG output, the test engineer must install cables to the Testhead, the VLSI Digital Tester, and the Tester Control Computer. When a device type that does not use the AWG is setup for testing, the cables must be removed.
Aside from interface issues, another disadvantage of using an AWG is cost. The cost of an AWG usually depends on the resolution of the waveform (or the number of samples per second) which it can process. The rise in costs of AWGs is often disproportional to the resolution of the waveform generated. The result can be a digital tester/AWG combination with a 1998 price tag of $1 million connected to a DUT priced at $2.
The present application discloses a method which allows an inexpensive circuit of resistors and capacitors to convert the output of digital tester drivers to a finite range of arbitrary waveforms. The generation of arbitrary waveforms takes place without an AWG.
A software application receives a set of datapoints which defines a waveform needed in the test program. The set of datapoints can be generated in a test simulator such as SPICE or can be generated by digitizing the arbitrary waveform needed in the test program. The software, based on the set of datapoints, determines how many resistors of a pseudo arbitrary waveform generator (PAWG) circuit need to be driven high in order to reproduce the waveform for input into the DUT. The software also determines the resolution, e.g., 5 ns, of the waveform. Once these calculations are complete, a set of digital vectors is created which describes to the VLSI digital tester how and when to drive the resistors. The vector set generated must be in a language accepted by the target VLSI tester.
As the vector set is processed, the resistors of the PAWG circuit cause the voltage at the output of the circuit to modulate. A capacitor connected to the resistors smooths the modulation creating a waveform substantially similar to that described by the set of datapoints. The output of the circuit (the test stimulus) is then applied to the DUT.